Hello, I'm attempting to run an LVS on a cell that contains a resistor and a MOScap using IBM's CMOS6RF process. The results come back as everything is fine except that the 'mSwitch' parameter of the resistor in the schematic is 0 and in the layout is 1e-55. This is apparently some kind of multiplicity parameter, and I clearly don't care about this level of discrepancy. Would anybody happen to know how to tell Assura to ignore these kinds of discrepancies? Thanks, Jake