AMIS C5 process

Discussion in 'Cadence' started by horridnoodle, Apr 12, 2006.

  1. horridnoodle

    horridnoodle Guest

    I am using the AMIS C5 process, and the Assuara rules for the drc lvs
    and rcx. I am using poly to poly capacitors in my layout which are the
    ones that were provided by Mosis as the AMIS device_examples. These
    caps pass the drc just fine. However, from what I have seen there is no
    corrisponding symbol in schematic for these poly to poly caps so the
    LVS will not pass, and just gives a component mismatch. The layout
    component is cap_pp. Has anyone else encountered this problem. If so,
    how did they get around it.

    Thanks
     
    horridnoodle, Apr 12, 2006
    #1
  2. horridnoodle

    horridnoodle Guest

    Thanks very much.
    I will give it a try.
     
    horridnoodle, Apr 14, 2006
    #2
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