AHDL vs. Veriloga

Discussion in 'Cadence' started by Kuan Zhou, Jul 7, 2003.

  1. Kuan Zhou

    Kuan Zhou Guest

    I am making some codes for mixed-signal blocks.However,
    I am facing a choice which language to use in Cadence.
    Some people told me Veriloga is better than AHDL.Which is used
    more in Industry?
    I want to replace some blocks by codes, then my simulation
    can run faster and the logic can be easily verified.

    Thank you very much!

    Kuan Zhou, Jul 7, 2003
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  2. Kuan Zhou

    Erik Wanta Guest

    By ahdl, I assume you mean spectreHDL. Given the choice, I would
    definitely go with veriloga as it is an IEEE standard.

    Cadence supplies some sample libraries with veriloga code. They are
    as follows:

    Look for the rfLib guide and behavioral models tutorial in the Cadence

    Cadence also has a tool called modelwriter that can create some simple
    veriloga blocks.
    Erik Wanta, Jul 8, 2003
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