AHDL vs. Veriloga

Discussion in 'Cadence' started by Kuan Zhou, Jul 7, 2003.

  1. Kuan Zhou

    Kuan Zhou Guest

    Hi,
    I am making some codes for mixed-signal blocks.However,
    I am facing a choice which language to use in Cadence.
    Some people told me Veriloga is better than AHDL.Which is used
    more in Industry?
    I want to replace some blocks by codes, then my simulation
    can run faster and the logic can be easily verified.


    Thank you very much!


    sincerely
     
    Kuan Zhou, Jul 7, 2003
    #1
    1. Advertisements

  2. Kuan Zhou

    Erik Wanta Guest

    Kuan:
    By ahdl, I assume you mean spectreHDL. Given the choice, I would
    definitely go with veriloga as it is an IEEE standard.

    Cadence supplies some sample libraries with veriloga code. They are
    as follows:
    $CDSHOME/tools/dfII/samples/artist/aExamples
    $CDSHOME/tools/dfII/samples/artist/ahdlLib
    $CDSHOME/tools/dfII/samples/artist/rfExamples
    $CDSHOME/tools/dfII/samples/artist/rfLib
    $CDSHOME/tools/dfII/samples/artist/pllLib

    Look for the rfLib guide and behavioral models tutorial in the Cadence
    documentation.

    Cadence also has a tool called modelwriter that can create some simple
    veriloga blocks.
     
    Erik Wanta, Jul 8, 2003
    #2
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.