Cadence

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  1. analogIC

    PoleZero VS. AC analysis in Spectre

    analogIC, Apr 19, 2011
    Replies:
    1
    Views:
    1,157
    Andrew Beckett
    Apr 22, 2011
  2. mvalery

    Connectivity Mark Net for temporary layers

    mvalery, Apr 27, 2011
    Replies:
    0
    Views:
    999
    mvalery
    Apr 27, 2011
  3. EDPHWSW

    Spicy Schematics for iPad

    EDPHWSW, Apr 29, 2011
    Replies:
    0
    Views:
    935
    EDPHWSW
    Apr 29, 2011
  4. Sam

    Noise Analysis

    Sam, Apr 30, 2011
    Replies:
    0
    Views:
    941
    Sam
    Apr 30, 2011
  5. Gio

    errset command question

    Gio, May 7, 2011
    Replies:
    1
    Views:
    944
    Andrew Beckett
    May 8, 2011
  6. Debjit Pal

    Unable to create parallel thread of execution with fork join

    Debjit Pal, May 9, 2011
    Replies:
    0
    Views:
    1,004
    Debjit Pal
    May 9, 2011
  7. GS

    bbox of instance in schematic

    GS, May 18, 2011
    Replies:
    1
    Views:
    1,013
    Marcel Preda
    May 19, 2011
  8. zhouk01

    adding XA in analog artist

    zhouk01, May 20, 2011
    Replies:
    0
    Views:
    839
    zhouk01
    May 20, 2011
  9. Sam

    PZ Analysis on Verilog A Model

    Sam, May 4, 2011
    Replies:
    1
    Views:
    915
    Kenneth Brun Nielsen
    May 20, 2011
  10. leo1408

    Invalid dev or device instance in dc analysis

    leo1408, May 21, 2011
    Replies:
    0
    Views:
    951
    leo1408
    May 21, 2011
  11. Rick Mattern

    voltage storm filtering presistors

    Rick Mattern, May 24, 2011
    Replies:
    0
    Views:
    924
    Rick Mattern
    May 24, 2011
  12. Tarek

    RHEL6 support?

    Tarek, May 20, 2011
    Replies:
    1
    Views:
    1,065
    Andrew Beckett
    Jun 1, 2011
  13. Marcel Preda

    dbCreateProp , and type have to be a dbObjId

    Marcel Preda, May 25, 2011
    Replies:
    5
    Views:
    1,473
    Marcel Preda
    Jun 3, 2011
  14. Paul Shepherd

    Displaying CDF parameter based on cell type?

    Paul Shepherd, May 26, 2011
    Replies:
    2
    Views:
    1,006
    Paul Shepherd
    Jun 7, 2011
  15. Marcel Preda

    merge all shapes on a specific layer

    Marcel Preda, Jun 8, 2011
    Replies:
    1
    Views:
    1,400
    Andrew Beckett
    Jun 9, 2011
  16. Konx

    RTL Compiler: loading of "schematics"

    Konx, Jun 17, 2011
    Replies:
    0
    Views:
    928
    Konx
    Jun 17, 2011
  17. FraNi

    noise analysis in IC61

    FraNi, Jun 21, 2011
    Replies:
    1
    Views:
    937
    Sohaib Saadat Afridi
    Jun 22, 2011
  18. aero

    Segmentation fault on solaris 10 sparc

    aero, Jun 28, 2011
    Replies:
    1
    Views:
    1,436
    Andrew Beckett
    Jul 1, 2011
  19. murtuza shariff

    Subject : LinkedIn Event: Web Application Conference

    murtuza shariff, Jul 2, 2011
    Replies:
    0
    Views:
    896
    murtuza shariff
    Jul 2, 2011
  20. David Kubalek

    Crash during loading of large (~3GB) av_extracted file

    David Kubalek, Jul 4, 2011
    Replies:
    2
    Views:
    809
    Andrew Beckett
    Jul 5, 2011
  21. Konx

    Cadence Encounter: set the cell orientation

    Konx, Jul 12, 2011
    Replies:
    0
    Views:
    995
    Konx
    Jul 12, 2011
  22. sg

    string 2 list

    sg, Jul 10, 2011
    Replies:
    2
    Views:
    855
    Pete Z.
    Jul 19, 2011
  23. Rick Mattern

    skill syntax question

    Rick Mattern, Jul 22, 2011
    Replies:
    1
    Views:
    849
    Marcel Preda
    Jul 24, 2011
  24. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    0
    Views:
    2,277
    I-F AB
    Jul 28, 2011
  25. Rick Mattern

    skill to access ADEXL options

    Rick Mattern, Jul 28, 2011
    Replies:
    0
    Views:
    952
    Rick Mattern
    Jul 28, 2011
  26. pforPDK

    what are good checks to verify applied CDF on a device symbol in schematic

    pforPDK, Jun 15, 2011
    Replies:
    1
    Views:
    888
    I-F AB
    Aug 1, 2011
  27. Dennis Blau

    velocity: multiple identical partitions

    Dennis Blau, Aug 1, 2011
    Replies:
    1
    Views:
    897
    Dennis Blau
    Aug 2, 2011
  28. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    2
    Views:
    1,120
    I-F AB
    Aug 3, 2011
  29. KLARO

    Allegro expand flag ?

    KLARO, Aug 8, 2011
    Replies:
    0
    Views:
    940
    KLARO
    Aug 8, 2011
  30. Hannes

    Use of compare_model_timing in SoC Encounter

    Hannes, Aug 10, 2011
    Replies:
    0
    Views:
    807
    Hannes
    Aug 10, 2011
  31. sg_vlsi

    Reg:Change via property in IC613

    sg_vlsi, Aug 8, 2011
    Replies:
    3
    Views:
    991
    Andrew Beckett
    Aug 12, 2011
  32. Rene

    VHDL import error message

    Rene, Aug 12, 2011
    Replies:
    0
    Views:
    956
    Rene
    Aug 12, 2011
  33. Rick Mattern

    simulation is still running but the ade-xl believes it has finished

    Rick Mattern, Aug 15, 2011
    Replies:
    0
    Views:
    873
    Rick Mattern
    Aug 15, 2011
  34. jren

    cdf lost every time I log out from cadence

    jren, Aug 25, 2011
    Replies:
    4
    Views:
    1,142
    jren
    Aug 25, 2011
  35. bsrin

    CIW banner labels are missing

    bsrin, Aug 19, 2011
    Replies:
    1
    Views:
    1,051
    Pete Z.
    Aug 25, 2011
  36. sg

    Shorted signals

    sg, Aug 29, 2011
    Replies:
    1
    Views:
    981
    sg
    Aug 29, 2011
  37. PolyPusher

    Using Skill to change properties on fets..

    PolyPusher, Aug 31, 2011
    Replies:
    3
    Views:
    1,657
    PolyPusher
    Sep 6, 2011
  38. Poojan Wagh

    UWI format and branches, attributes

    Poojan Wagh, Sep 12, 2011
    Replies:
    1
    Views:
    1,064
    Poojan Wagh
    Sep 12, 2011
  39. jren

    stretch handle accessed by parent cell

    jren, Sep 14, 2011
    Replies:
    0
    Views:
    1,049
    jren
    Sep 14, 2011
  40. jmss

    ADE vs OSS netlisting

    jmss, Aug 25, 2011
    Replies:
    2
    Views:
    1,539
    jmss
    Sep 19, 2011
  41. vivek

    Avoid encounter from inserting buffer in a net by breaking the connection.

    vivek, Sep 21, 2011
    Replies:
    0
    Views:
    918
    vivek
    Sep 21, 2011
  42. jren

    precision of float

    jren, Sep 6, 2011
    Replies:
    3
    Views:
    1,198
    Andrew Beckett
    Sep 26, 2011
  43. Paul Shepherd

    Netlisting resistors and capacitors through HNL for hspice?

    Paul Shepherd, Sep 9, 2011
    Replies:
    2
    Views:
    1,262
    Andrew Beckett
    Sep 26, 2011
  44. Kenneth Brun Nielsen

    Emacs SKILL mode

    Kenneth Brun Nielsen, May 2, 2011
    Replies:
    3
    Views:
    1,783
    [email protected]
    Oct 4, 2011
  45. Jie

    choose all identical shapes in two layers in divaDRC.rul DRC check

    Jie, Oct 6, 2011
    Replies:
    0
    Views:
    1,039
    Jie
    Oct 6, 2011
  46. santom_cs

    Finding Ft in Cadence

    santom_cs, Nov 10, 2011
    Replies:
    0
    Views:
    1,175
    santom_cs
    Nov 10, 2011
  47. PolyPusher

    center point of overlapping bounding boxes

    PolyPusher, Oct 11, 2011
    Replies:
    1
    Views:
    1,161
    Andrew Beckett
    Nov 11, 2011
  48. Robert Rudolf

    slow MC simulations when varying temperature

    Robert Rudolf, Oct 14, 2011
    Replies:
    2
    Views:
    1,361
    Robert Rudolf
    Nov 16, 2011
  49. hamidrezah

    Two question on Layouts in Cadence

    hamidrezah, Nov 11, 2011
    Replies:
    3
    Views:
    1,245
    Andrew Beckett
    Nov 16, 2011
  50. hamidrezah

    Parasitic Extracted Capacitors: Coordinates

    hamidrezah, Nov 15, 2011
    Replies:
    1
    Views:
    1,100
    Andrew Beckett
    Nov 16, 2011
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