Cadence

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  1. hamidrezah

    Two question on Layouts in Cadence

    hamidrezah, Nov 11, 2011
    Replies:
    3
    Views:
    1,511
    Andrew Beckett
    Nov 16, 2011
  2. Robert Rudolf

    slow MC simulations when varying temperature

    Robert Rudolf, Oct 14, 2011
    Replies:
    2
    Views:
    1,627
    Robert Rudolf
    Nov 16, 2011
  3. PolyPusher

    center point of overlapping bounding boxes

    PolyPusher, Oct 11, 2011
    Replies:
    1
    Views:
    1,366
    Andrew Beckett
    Nov 11, 2011
  4. santom_cs

    Finding Ft in Cadence

    santom_cs, Nov 10, 2011
    Replies:
    0
    Views:
    1,439
    santom_cs
    Nov 10, 2011
  5. Jie

    choose all identical shapes in two layers in divaDRC.rul DRC check

    Jie, Oct 6, 2011
    Replies:
    0
    Views:
    1,235
    Jie
    Oct 6, 2011
  6. Kenneth Brun Nielsen

    Emacs SKILL mode

    Kenneth Brun Nielsen, May 2, 2011
    Replies:
    3
    Views:
    2,043
    [email protected]
    Oct 4, 2011
  7. Paul Shepherd

    Netlisting resistors and capacitors through HNL for hspice?

    Paul Shepherd, Sep 9, 2011
    Replies:
    2
    Views:
    1,504
    Andrew Beckett
    Sep 26, 2011
  8. jren

    precision of float

    jren, Sep 6, 2011
    Replies:
    3
    Views:
    1,393
    Andrew Beckett
    Sep 26, 2011
  9. vivek

    Avoid encounter from inserting buffer in a net by breaking the connection.

    vivek, Sep 21, 2011
    Replies:
    0
    Views:
    1,127
    vivek
    Sep 21, 2011
  10. jmss

    ADE vs OSS netlisting

    jmss, Aug 25, 2011
    Replies:
    2
    Views:
    1,806
    jmss
    Sep 19, 2011
  11. jren

    stretch handle accessed by parent cell

    jren, Sep 14, 2011
    Replies:
    0
    Views:
    1,186
    jren
    Sep 14, 2011
  12. Poojan Wagh

    UWI format and branches, attributes

    Poojan Wagh, Sep 12, 2011
    Replies:
    1
    Views:
    1,186
    Poojan Wagh
    Sep 12, 2011
  13. PolyPusher

    Using Skill to change properties on fets..

    PolyPusher, Aug 31, 2011
    Replies:
    3
    Views:
    1,995
    PolyPusher
    Sep 6, 2011
  14. sg

    Shorted signals

    sg, Aug 29, 2011
    Replies:
    1
    Views:
    1,101
    sg
    Aug 29, 2011
  15. bsrin

    CIW banner labels are missing

    bsrin, Aug 19, 2011
    Replies:
    1
    Views:
    1,273
    Pete Z.
    Aug 25, 2011
  16. jren

    cdf lost every time I log out from cadence

    jren, Aug 25, 2011
    Replies:
    4
    Views:
    1,441
    jren
    Aug 25, 2011
  17. Rick Mattern

    simulation is still running but the ade-xl believes it has finished

    Rick Mattern, Aug 15, 2011
    Replies:
    0
    Views:
    1,112
    Rick Mattern
    Aug 15, 2011
  18. Rene

    VHDL import error message

    Rene, Aug 12, 2011
    Replies:
    0
    Views:
    1,127
    Rene
    Aug 12, 2011
  19. sg_vlsi

    Reg:Change via property in IC613

    sg_vlsi, Aug 8, 2011
    Replies:
    3
    Views:
    1,199
    Andrew Beckett
    Aug 12, 2011
  20. Hannes

    Use of compare_model_timing in SoC Encounter

    Hannes, Aug 10, 2011
    Replies:
    0
    Views:
    986
    Hannes
    Aug 10, 2011
  21. KLARO

    Allegro expand flag ?

    KLARO, Aug 8, 2011
    Replies:
    0
    Views:
    1,107
    KLARO
    Aug 8, 2011
  22. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    2
    Views:
    1,405
    I-F AB
    Aug 3, 2011
  23. Dennis Blau

    velocity: multiple identical partitions

    Dennis Blau, Aug 1, 2011
    Replies:
    1
    Views:
    1,093
    Dennis Blau
    Aug 2, 2011
  24. pforPDK

    what are good checks to verify applied CDF on a device symbol in schematic

    pforPDK, Jun 15, 2011
    Replies:
    1
    Views:
    1,076
    I-F AB
    Aug 1, 2011
  25. Rick Mattern

    skill to access ADEXL options

    Rick Mattern, Jul 28, 2011
    Replies:
    0
    Views:
    1,209
    Rick Mattern
    Jul 28, 2011
  26. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    0
    Views:
    2,716
    I-F AB
    Jul 28, 2011
  27. Rick Mattern

    skill syntax question

    Rick Mattern, Jul 22, 2011
    Replies:
    1
    Views:
    1,046
    Marcel Preda
    Jul 24, 2011
  28. sg

    string 2 list

    sg, Jul 10, 2011
    Replies:
    2
    Views:
    987
    Pete Z.
    Jul 19, 2011
  29. Konx

    Cadence Encounter: set the cell orientation

    Konx, Jul 12, 2011
    Replies:
    0
    Views:
    1,237
    Konx
    Jul 12, 2011
  30. David Kubalek

    Crash during loading of large (~3GB) av_extracted file

    David Kubalek, Jul 4, 2011
    Replies:
    2
    Views:
    942
    Andrew Beckett
    Jul 5, 2011
  31. murtuza shariff

    Subject : LinkedIn Event: Web Application Conference

    murtuza shariff, Jul 2, 2011
    Replies:
    0
    Views:
    1,088
    murtuza shariff
    Jul 2, 2011
  32. aero

    Segmentation fault on solaris 10 sparc

    aero, Jun 28, 2011
    Replies:
    1
    Views:
    1,642
    Andrew Beckett
    Jul 1, 2011
  33. FraNi

    noise analysis in IC61

    FraNi, Jun 21, 2011
    Replies:
    1
    Views:
    1,095
    Sohaib Saadat Afridi
    Jun 22, 2011
  34. Konx

    RTL Compiler: loading of "schematics"

    Konx, Jun 17, 2011
    Replies:
    0
    Views:
    1,083
    Konx
    Jun 17, 2011
  35. Marcel Preda

    merge all shapes on a specific layer

    Marcel Preda, Jun 8, 2011
    Replies:
    1
    Views:
    1,874
    Andrew Beckett
    Jun 9, 2011
  36. Paul Shepherd

    Displaying CDF parameter based on cell type?

    Paul Shepherd, May 26, 2011
    Replies:
    2
    Views:
    1,252
    Paul Shepherd
    Jun 7, 2011
  37. Marcel Preda

    dbCreateProp , and type have to be a dbObjId

    Marcel Preda, May 25, 2011
    Replies:
    5
    Views:
    1,762
    Marcel Preda
    Jun 3, 2011
  38. Tarek

    RHEL6 support?

    Tarek, May 20, 2011
    Replies:
    1
    Views:
    1,238
    Andrew Beckett
    Jun 1, 2011
  39. Rick Mattern

    voltage storm filtering presistors

    Rick Mattern, May 24, 2011
    Replies:
    0
    Views:
    1,114
    Rick Mattern
    May 24, 2011
  40. leo1408

    Invalid dev or device instance in dc analysis

    leo1408, May 21, 2011
    Replies:
    0
    Views:
    1,152
    leo1408
    May 21, 2011
  41. Sam

    PZ Analysis on Verilog A Model

    Sam, May 4, 2011
    Replies:
    1
    Views:
    1,034
    Kenneth Brun Nielsen
    May 20, 2011
  42. zhouk01

    adding XA in analog artist

    zhouk01, May 20, 2011
    Replies:
    0
    Views:
    1,073
    zhouk01
    May 20, 2011
  43. GS

    bbox of instance in schematic

    GS, May 18, 2011
    Replies:
    1
    Views:
    1,259
    Marcel Preda
    May 19, 2011
  44. Debjit Pal

    Unable to create parallel thread of execution with fork join

    Debjit Pal, May 9, 2011
    Replies:
    0
    Views:
    1,259
    Debjit Pal
    May 9, 2011
  45. Gio

    errset command question

    Gio, May 7, 2011
    Replies:
    1
    Views:
    1,141
    Andrew Beckett
    May 8, 2011
  46. Sam

    Noise Analysis

    Sam, Apr 30, 2011
    Replies:
    0
    Views:
    1,106
    Sam
    Apr 30, 2011
  47. EDPHWSW

    Spicy Schematics for iPad

    EDPHWSW, Apr 29, 2011
    Replies:
    0
    Views:
    1,173
    EDPHWSW
    Apr 29, 2011
  48. mvalery

    Connectivity Mark Net for temporary layers

    mvalery, Apr 27, 2011
    Replies:
    0
    Views:
    1,183
    mvalery
    Apr 27, 2011
  49. analogIC

    PoleZero VS. AC analysis in Spectre

    analogIC, Apr 19, 2011
    Replies:
    1
    Views:
    1,323
    Andrew Beckett
    Apr 22, 2011
  50. Nilay

    'freq' parameter in ac analysis

    Nilay, Apr 20, 2011
    Replies:
    1
    Views:
    1,185
    Andrew Beckett
    Apr 22, 2011
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