Dear All I need some help to understand more about latch up failure. Usually, latch up failure happens are due to improper layout of design OR due to process issue? I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is the W/L bigger than normal logic mos or some other reason? If anyone has any good reference on this topic, kindly share with me. Thank you for your help. best rgds Jason